我正在尝试为部分产品生成器编写VHDL代码。代码如下:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use ieee.numeric_std.all;
entity boothencoder_ppg is
port(Y: in std_logic_vector(53 downto 1);
     X: in std_logic_vector(53 downto 1);
     PPG: out std_logic_vector(53 downto 1)
     );
end boothencoder_ppg;
architecture behavioral of boothencoder_ppg is
signal U, SFT, W, M, A: std_logic;
    begin
    for m in 1 to 53 loop
    U = Y(m+1) xnor Y(m);
    SFT = Y(m-1) xnor Y(m);
    W = U and SFT;
    M = SFT? X(m-1) : X(m);
    A = M xor Y(m+1);
    PPG = A nor W;
    end loop;
end behavioral;

最佳答案

VHDL中的信号分配运算符写为:

a <= b;

https://stackoverflow.com/questions/13577780/